Forming reliable multi-level metal interconnections is a key technology to integrated devices in organic integrated circuits (ICs). The conventional approach, called "via-hole", locally removes the insulator and makes metal interconnects through the holes. Due to the high sensitivity of organic materials to chemical solvents, heat, and photo-radiation used in conventional "via-hole" methods, alternative printing methods or laser drilling methods have been developed, but a reliable and practical metal interconnection in organic ICs is still challenging.

The collaboration of a KAIST research team led by Professors Sung Gap Im and Postech research team led by Professor Kim Jae-Joon suggested and reported a new interconnection method excluding via-hole formation, "via-hole-less metal interconnection", in Nature Communications on June 3, 2019. Metal electrodes in different layers can be isolated from each other by patterned dielectric layers whereas they can be interconnected to others in the open area where the dielectric layer is not present (see the image below).

Vapor phase deposition and in-situ patterning of a dielectric layer using iCVD (initiated chemical vapor deposition), used in the "via-hole-less" method, ensure the damage-free process to organic semiconductor materials and results in the preserved outstanding performance of the organic devices while multilevel metal interconnects are formed. The collaboration team successfully demonstrated three-dimensional stacking of 5 organic transistors and integrated circuits consisting of them using the proposed via-hole-less interconnect method (see the image below).

Prof. Im said "Our proposed via-hole-less interconnect method using a selectively patterned dielectric overcomes the limitations of previous time-consuming one-by-one via-hole formation process and provided reliable methods for metal interconnects in organic ICs. We expect the via-hole-less scheme to bring an advance in the organic IC technology."